Add a new PM CPU ops driver for ARM Fixed Virtual Platform (FVP) that
enables bare metal SMP support without ARM Trusted Firmware (ATF).

The driver provides CPU power-on and system reset operations by directly
interfacing with FVP's power controller (PWRC) and V2M system registers.

The implementation includes RVBAR_EL3 configuration to redirect
secondary CPU reset vectors to Zephyr's image header, enabling
proper SMP initialization without firmware assistance.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

This adds necessary configuration files to build with SMP and no trusted
firmware. Given PSCI is not available, CPU power management uses the FVP
power controller directly.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Reorganize fvp_aemv8a SOC into unified fvp_aem series with a v8a
architecture variants to enable cleaner board target naming. This also
sets the stage for upcoming ARMv9-A support.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Create unified board configuration to replace verbose board naming
with shorter hierarchical structure. This board works with the new
unified fvp_aem SOC series and supports the v8a architecture variant.

This enables board targets like:
- fvp_base_revc_2xaem/v8a (basic ARMv8-A)
- fvp_base_revc_2xaem/v8a/smp (ARMv8-A SMP)
- fvp_base_revc_2xaem/v8a/smp/ns (ARMv8-A SMP non-secure)

The structure replaces the existing overly verbose board with a cleaner,
more maintainable organization and provides a foundation for adding v9a
variants.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add deprecated.cmake mappings to redirect old board names to new
unified structure:

- fvp_base_revc_2xaemv8a
→ fvp_base_revc_2xaem/v8a

- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp
→ fvp_base_revc_2xaem/v8a/smp

- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
→ fvp_base_revc_2xaem/v8a/smp/ns

This ensures existing build commands and documentation continue to work
with deprecation warnings while transitioning to the new board structure.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add ARMv9-A architecture support with Cortex-A510 CPU as the default
processor for generic ARMv9-A targets.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

New board targets:
- fvp_base_revc_2xaem/v9a (basic ARMv9-A single core)
- fvp_base_revc_2xaem/v9a/smp (ARMv9-A SMP 4 cores)
- fvp_base_revc_2xaem/v9a/smp/ns (ARMv9-A SMP non-secure with TFA)

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A
specific configuration parameters.

New board target:
- fvp_base_revc_2xaem/a320

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add comprehensive test to validate ARM64 architectural feature detection
across ARMv8.1 through ARMv9-A implementations, providing runtime
verification of processor capabilities and security features.

Core architecture features tested:
- Exception Level (EL) support detection (EL0-EL3)
- SVE (Scalable Vector Extension) presence and capabilities
- Advanced SIMD (NEON) and Floating Point implementation levels
- Architecture version classification (ARMv8 vs ARMv9-A)

ARMv8.1-A+ features:
- LSE (Large System Extensions) atomic operations with level detection
- Pointer Authentication (PAC) with comprehensive variant analysis:
  * API/APA (Address), GPI/GPA (Generic) authentication
  * Enhanced PAC levels (1, 3, 4, 5) with FPACCOMBINE detection
  * QARMA3 algorithm support (GPA3/APA3)

ARMv8.5-A+ security and performance features:
- Branch Target Identification (BTI) for control flow integrity
- Memory Tagging Extensions (MTE) with level classification
- Random Number Generation (RNDR) hardware entropy
- Speculative Store Bypass Safe (SSBS) side-channel mitigation

ARMv8.7-A+ advanced features:
- WFxT (Wait with Timeout) enhanced synchronization
- RPRES (Reciprocal Precision) optimized math operations

ARMv8.8-A+ features:
- MOPS (Memory Copy/Set) optimized memory operations
- BC (Branch Consistency) advanced branch handling

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Implement Scalable Vector Extension (SVE) context switching support,
enabling threads to use SVE instructions with lazy context preservation
across task switches.

The implementation is incremental: if only FPU instructions are used
then only the NEON access is granted and preserved to minimize context
switching overhead. If SVE is used then the NEON context is upgraded to
SVE and then full SVE access is granted and preserved from that point
onwards.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add test to validate SVE (Scalable Vector Extension) context switching
implementation, ensuring proper register preservation across thread
switches in multi-threaded environments.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Expand the SVE context switching test to cover all thread privilege
combinations with validation of SVE state preservation across different
contexts.

Test Coverage:
- Privileged vs Privileged threads (kernel mode)
- User vs User threads (userspace with memory domains)
- User vs Privileged threads (mixed privilege levels)

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

This fixes the following:

CMakeStyle File:cmake/gcc-m-cpu.cmake Line:7
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:22
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:28
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:38
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:48
Column:Remove space before '(' in if() statements

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Use Inner Shareable (IS) TLB invalidation instructions in SMP
configurations to broadcast TLB invalidations to all CPUs.

Use TLBI VMALLE1IS instead of VMALLE1 in invalidate_tlb_all().

While at it, implement proper page-specific invalidation using TLBI VAE1IS
in invalidate_tlb_page() instead of falling back to full invalidation.

This fixes many SMP test failures with userspace enabled.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

The MPSC test consumer was incorrectly handling node returns to
producer free queues. It called spsc_acquire() without checking the
return value, then unconditionally called spsc_produce(). When the
SPSC free queue was full, spsc_acquire() would return NULL and not
increment the acquire counter, causing spsc_produce() to silently do
nothing (it only produces if acquire > 0). This resulted in lost nodes.

At least on QEMU, a 4-CPU configuration is needed for this bug to manifest.
Producers put all nodes in flight simultaneously with the single consumer
unable to keep up, causing frequent SPSC queue full conditions.

The Fix: Loop on spsc_acquire() until it succeeds before calling
spsc_produce(). This ensures nodes are always successfully returned to
producer queues.

Added board overlay for qemu_cortex_a53/smp to enable 4-CPU testing,
which reproduces the issue and validates the fix.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

On ARM64 SMP systems, tight polling loops on atomic variables can fail
to observe updates from other CPUs due to cache coherency issues, even
when using atomic operations with acquire/release semantics.

ARM64 atomic_get() compiles to LDAR (load-acquire), which provides
memory ordering semantics but does NOT force cache coherency on every
iteration in a tight loop. In the following pattern:

    while (atomic_get(&flag) == 0) { /* spin */ }

The CPU can satisfy the LDAR from its local cache without running the
cache coherency protocol, causing it to never see updates written by
other CPUs. Acquire/release semantics provide ordering guarantees but
not cache invalidation forcing.

Add explicit DMB (Data Memory Barrier) before atomic loads in the
lockfree library's SMP accessor macros:

- mpsc_ptr_get(): Add barrier_dmem_fence_full() before atomic_ptr_get()
- z_spsc_in(): Add barrier before atomic_get()
- z_spsc_out(): Add barrier before atomic_get()

The DMB forces completion of the cache coherency protocol, ensuring
pending cache invalidations from other CPUs are processed before the
atomic read, guaranteeing fresh data is observed.

Zephyr's scheduler already uses this pattern in kernel/sched.c:149
where barrier_dmem_fence_full() is used with the comment:
"Other cpus spin on this locklessly!"

The lockfree test with 4 CPUs hung indefinitely on ARM FVP without
these barriers but passes immediately with them. QEMU works without
barriers due to simpler cache coherency simulation.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>